III-V Heterostructure Nanowire Tunnel FETs

In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from...

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Veröffentlicht in:	IEEE journal of the Electron Devices Society 2015-05, Vol.3 (3), p.96-102
Hauptverfasser:	Lind, Erik, Memisevic, Elvedin, Dey, Anil W., Wernersson, Lars-Erik
Format:	Artikel
Sprache:	eng
Schlagworte:	Annan elektroteknik och elektronik broken gap Electrical Engineering, Electronic Engineering, Information Engineering Elektroteknik och elektronik Engineering and Technology GaSb III-V InAs Logic gates Nanoscale devices Other Electrical Engineering, Electronic Engineering, Information Engineering Photonic band gap Silicon Substrates Teknik Temperature measurement Tunnel field effect transistors (TFET) Tunneling
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Beschreibung
Zusammenfassung:	In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from lateral InAs/GaSb are shown, as well as first results on integration of vertical InAs/GaSb nanowire TFETs on Si substrates.
ISSN:	2168-6734 2168-6734
DOI:	10.1109/JEDS.2015.2388811