Dielectric interface engineering using aminosilane coupling agent for enhancement of negative differential resistance phenomenon

Negative differential resistance (NDR) devices have recently attracted interest as multi-valued logic (MVL) circuits, owing to their folded electrical characteristics. However, with necessity of sophisticated computing systems, advanced NDR devices are required for stable low-power-consumption MVL c...

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Veröffentlicht in:Materials today advances 2024-03, Vol.21, p.100475, Article 100475
Hauptverfasser: Han, Kyu Hyun, Kim, Seung-Geun, Kim, Seung-Hwan, Kim, Jong-Hyun, Hwang, Seong-Hyun, Kim, Min-Su, Song, Sung-Joo, Yu, Hyun-Yong
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Sprache:eng
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Zusammenfassung:Negative differential resistance (NDR) devices have recently attracted interest as multi-valued logic (MVL) circuits, owing to their folded electrical characteristics. However, with necessity of sophisticated computing systems, advanced NDR devices are required for stable low-power-consumption MVL circuits. Here, we developed van der Waals (vdW) NDR device with high peak-to-valley current ratio (PVCR) and low peak voltage (Vpeak), utilizing the passivation and doping effects of APTES layer as aminosilane coupling agent, at dielectric interface. The PVCR of NDR device reached 10 through reduced interface trap owing to the passivation effect of APTES silane group. Additionally, low Vpeak of NDR device was achieved at 0.2 V through doping effect of the APTES amine group. These PVCR and Vpeak values indicate the one of the best vdW NDR performance. Furthermore, stable logic state and low operation voltage of the ternary inverter were implemented using NDR device with high PVCR and low Vpeak. This NDR device represents a significant advancement for next-generation MVL technologies. An NDR device with high peak-to-valley current ratio (PVCR) and low peak voltage (Vpeak) was developed, utilizing the passivation and doping effects of aminosilane coupling agent, at dielectric interface. The NDR device have achieved the PVCR of 10 and the Vpeak of 0.2 V, and implemented ternary logic. [Display omitted]
ISSN:2590-0498
2590-0498
DOI:10.1016/j.mtadv.2024.100475