Approximate 8-bit multipliers and their physical design implementation

•In this article we design 4 × 4 multipliers using 4:2 compressors and encoded partial products. We then propose the use of an approximate 3-bit adder to calculate the sum of partial products obtained from the 4×4 multipliers in less significant positions in order to construct approximate 8×8 multipliers. The proposed designs are then synthesized using Cadence Design Suite for a 45-nm standard cell library.•The remainder of the article describes the Physical Design flow from the gate level net-list to final GDS-II using the open-source Physical Design flow tool Q-flow. Approximate computing is widely used in a large number of error-tolerant applications. Multiplication is an integral arithmetic operation for many of these applications. In this paper we discuss 8 bit multiplier designs designed using approximate 4:2 compressors and encoded sum of partial products, and later introduce an approximate full adder to compute the sum of partial products in less significant bit positions. We use these techniques to systematically trade off accuracy for improvements in area, power and more significantly delay. These multipliers were designed using Verilog and synthesized using Cadence Design Suite with the help of a 45nm standard cell library. The physical designs of exact, existing and proposed multipliers were also performed using the open source RTL to GDS flow tool Q-flow. This is done to highlight the importance and reliability of open source tools in the VLSI physical design process when compared to paid software which may not be accessible to everyone.