Stencil lithography for bridging MEMS and NEMS

The damage inflicted to silicon nanowires (Si NWs) during the HF vapor etch release poses a challenge to the monolithic integration of Si NWs with higher-order structures, such as microelectromechanical systems (MEMS). This paper reports the development of a stencil lithography-based protection technology that protects Si NWs during prolonged HF vapor release and enables their MEMS integration. Besides, a simplified fabrication flow for the stencil is presented offering ease of patterning of backside features on the nitride membrane. The entire process on Si NW can be performed in a resistless manner. HF vapor etch damage to the Si NWs is characterized, followed by the calibration of the proposed technology steps for Si NW protection. The stencil is fabricated and the developed technology is applied on a Si NW-based multiscale device architecture to protectively coat Si NWs in a localized manner. Protection of Si NW under a prolonged (>3 h) HF vapor etch process has been achieved. Moreover, selective removal of the protection layer around Si NW is demonstrated at the end of the process. The proposed technology also offers access to localized surface modifications on a multiscale device architecture for biological or chemical sensing applications. [Display omitted] •Characterization of HF vapor etch damage to monolithic silicon nanowire.•Development of a novel stencil lithography-based technology.•Development of a new stencil fabrication flow for silicon nanowire protection against prolonged HF vapor etching.•Technology offers access to localized surfaces on a multiscale architecture enabling easier MEMS and NEMS integration.