Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms

As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilitie...

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Veröffentlicht in:npj quantum information 2022-08, Vol.8 (1), p.1-7, Article 93
Hauptverfasser: Verjauw, J., Acharya, R., Van Damme, J., Ivanov, Ts, Lozano, D. Perez, Mohiyaddin, F. A., Wan, D., Jussot, J., Vadiraj, A. M., Mongillo, M., Heyns, M., Radu, I., Govoreanu, B., Potočnik, A.
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Sprache:eng
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Zusammenfassung:As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.
ISSN:2056-6387
2056-6387
DOI:10.1038/s41534-022-00600-9