Study of HCI Reliability for PLDMOS

Study of HCI Reliability for PLDMOS

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are...

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Veröffentlicht in:MATEC web of conferences 2018-01, Vol.201, p.2001
Hauptverfasser: Deivasigamani, Ravi, Sheu, Gene, Aanand, Wei Lu, Shao, Sarwar Imam, Syed, Lai, Chiu-Chung, Yang, Shao-Ming
Format: Artikel
Sprache:eng
Schlagworte:
Carrier injection
Degradation
Electric potential
Hot electrons
Voltage
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Zusammenfassung:In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.
ISSN:2261-236X
2274-7214
2261-236X
DOI:10.1051/matecconf/201820102001