CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance

•A novel method is proposed for the design of ternary logic circuits using CNTFETs.•An improved version of the CNTFET-based THA and TMUL designs proposed.•The proposed THA/TMUL designs improved the delay, power, and PDP by 37.01 %/ 30.48 %, 14.07 %/ 6.64 %, and 45.87 %/ 36.74 % owing to a reduction of 54.44 %/ 45 % in transistors count, respectively, as an effective factor on the delay and power, compared to existing works.•The PVT variations for the proposed THA and TMUL are also analyzed and compared with the existing designs. Ternary logics are more desirable than the binary logic because it offers high speed operations and large density of information in digital logic systems. The carbon nanotube field-effect transistors (CNTFETs) are considered as better option for designing the ternary circuits because it provides the multiple threshold voltages by changing nanotube diameter. The complex arithmetic schematics such as adders and multipliers are important circuits in many VLSI applications. The ternary half-adder (THA) and multiplier (TMUL) designed using the Stanford 32 nm CNTFET are proposed in this study. The proposed THA and TMUL uses 41 and 33 CNTFETs and that resulting in a 54.44 % and 45 % reduction in transistor count, which plays major role for delay and power optimization. As a result, the proposed THA shows 37.01 %, 14.07 %, and 45.87 % improvement in delay, power, and energy, whereas TMUL shows 30.48 %, 6.64 %, and 36.74 % improvement in delay, power and energy, respectively, compared to existing circuits. The proposed THA and TMUL are developed using HSPICE with 0.9 V as a supply voltage.