Low Voltage High Performance CMOS Current Mode Four-Quadrant Analog Multiplier Circuit

This paper describes a new CMOS current mode four-quadrant analog multiplier circuit. The proposed design is based on a high performance squarer cell, whose main core is realized by the up–down topology trans-linear loop using flipped voltage followers (FVF). The simulation results are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 µm CMOS process available from level 49 MOSIS at 25◦C with ± 0.75 V supply voltage. The proposed multiplier offers improved characteristics compared to the multipliers previously exposed in the literature. It has a wide dynamic range. The total harmonic distortion is about 0.42% at 1 kHz with peak-to-peak input current of 40 µA. The −3 dB bandwidth is more than 850 MHz and a maximum power consumption is of approximately 105 µW.