High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

This research presents the optimization and proposal of P- and N-type 3-stacked Si Ge /Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si Ge FinFET, and Si Ge /Si SL FinFET, were comprehensively compared with HfO = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si Ge /Si SL FinFET exhibited the lowest average subthreshold slope (SS ) of 88 mV/dec, the highest maximum transconductance (G ) of 375.2 μS/μm, and the highest ON-OFF current ratio (I /I ), approximately 10 at V = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal-oxide-semiconductor (CMOS) inverters, a maximum gain of 91 was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si Ge /Si super-lattice FinFET with the state of the art was also investigated. The proposed Si Ge /Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.