A push–pull FVF LDO with full‐spectrum PSR and fast transient response

A push–pull low‐dropout regulator based on flipped voltage follower is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The push‐current mode with 1.2‐V input and 1‐V output effectively drives load circuits that are sensitive to supply noise. The pull‐current one with 1.2‐V input and 0.2‐V output effectively drives load circuits that are sensitive to ground noise. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns transient response time over load current (IL) of 10 µA to 20 mA. The presented design achieves a fast transient response and a high‐frequency PSR with a low‐gain fast loop (loop‐I), and enhances the low‐frequency PSR and the line/load regulation with a high‐gain slow loop (loop‐II). Furthermore, the circuit features a load regulation less than 0.09 mV/mA over IL of 10 µA to 20 mA and a line regulation less than 0.01 mV/mV, within a 120‐mV ripple applied to supply/ground. This design consumes a 58‐µA quiescent current (IQ) in both push‐current and pull‐current modes. The low‐dropout regulator works well over the load capacitor (CL) of 0 to 30 pF. A push‐pull low‐dropout regulator (LDO) based on flipped voltage follower (FVF) is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The proposed LDO that is fully different from the existing designs, benefits noise‐sensitive wideband circuits that require a high PSR and a fast transient response. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns response time over load current (IL) of 10 µA to 20 mA