Coupling effects of interface charge trapping and polarization switching in HfO2-based ferroelectric field effect transistors

HfO2-based ferroelectric field-effect transistors (FeFETs) are regarded as one of the most promising non-volatile memory technologies in the future. However, the charge trapping phenomenon during the program/erase operation is still a challenge. In this work, we comprehensively investigate the behaviors of semiconductor/insulator interface charge trapping in HfO2-based FeFETs. Through analyzing the effects of the spatial distribution of interface traps and the polarization switching speed, the coupling effects of semiconductor/insulator interface charge trapping and polarization switching are recognized. We also find that the band tail state traps have much less influence on the electrical characteristics of the FeFETs than the deep level state traps. Through engineering the devices with band tail state traps with concentrations as small as possible, the influences of charge trapping could be effectively suppressed. Moreover, the gate voltage (VG) scanning rate has a significant influence on the interface charge trapping process due to the time dependent change of ferroelectric polarization. The largest memory window could be obtained by carefully choosing the VG scanning rate of the FeFETs based on the polarization switching speed. This work represents a key step for realizing highly reliable HfO2-based FeFETs.