TL multiplier - supplemental materials

This directory contains the Verilog sources of our paper,” A two-stage operand trimming approximate logarithmic multiplier”, which is currently under review.

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Bibliographische Detailangaben
1. Verfasser:	Pilipović, Ratko
Format:	Dataset
Sprache:	eng
Schlagworte:	Approximate computing Arithmetic circuit design Energy-efficient processing Logarithmic multiplier Mitchell's multiplier Other
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	This directory contains the Verilog sources of our paper,” A two-stage operand trimming approximate logarithmic multiplier”, which is currently under review.
DOI:	10.21227/cbmz-zz42