Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems

This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS ® testbed. The parallelization and c...

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Bibliographische Detailangaben
Hauptverfasser:	Font-Bach, Oriol, Bartzoudis, Nikolaos, Payaro, Miquel, Pascual-Iserte, Antonio
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Comunicacions mòbils Enginyeria de la telecomunicació Field programmable gate arrays Finite impulse response filters Interference Interference (Sound) Interferències Long-Term Evolution (Telecommunications) Long-term evolution (Telecomunicacions) OFDM Radiocomunicació i exploració electromagnètica Real-time systems Resource management Sincronització Synchronization Àrees temàtiques de la UPC
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Beschreibung
Zusammenfassung:	This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS ® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.
ISSN:	1946-147X 1946-1488
DOI:	10.1109/FPL.2013.6645585