Contributions to the design, development and evaluation of network processors for automotive zonal gateway controllers
Tesi amb continguts retallats per motius de confidencialitat Tesi amb menció de Doctorat Internacional i de Doctorat Industrial (English) This PhD dissertation analyzes the evolution of vehicular networks and focuses on the main network processing platform integrated in them: the Gateway (GW). First...
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Format: | Dissertation |
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Zusammenfassung: | Tesi amb continguts retallats per motius de confidencialitat
Tesi amb menció de Doctorat Internacional i de Doctorat Industrial
(English) This PhD dissertation analyzes the evolution of vehicular networks and focuses on the main network processing platform integrated in them: the Gateway (GW). First, a thorough analysis of state of the art technologies involved in vehicular networks is performed, leading to the definition of the requirements of future network processing platforms. Then, the available options in the
state of the art for network processing, both in industry and academia, are analyzed. This analysis shows a gap in this area: there is currently no architecture fulfilling all the requirements of future automotive GW controllers. Moreover, Hardware (HW) accelerators and custom processor design are identified as a key differentiation factor which boosts the performance of the devices. Linking the result of this analysis with the current trend towards application specific processors, this thesis proposes the novel Elastic Gateway (eGW) System on Chip (SoC) architecture as a high performance network processor for future zonal GW controllers. The proposed architecture aims at fulfilling the identified gap, advancing towards future GW SoC solutions. Elastic Gateway SoC concept aims at synthesizing a scalable and future-proof architecture embracing all new and already established functions and features demanded in a zonal gateway controller for the new era of mobility. The challenge now is not only to design the right processor that can meet the requirements available today, but also to make this design suitable for the future. For this reason, the modularity, flexibility, scalability and configurability of these future processors take, more than ever, a starring role in the early design stages. This thesis is also providing a complete lifecycle methodology for the design and validation of different network processing products based on the proposed eGW SoC architecture.
Throughout this work the architecture is evaluated from a functional perspective, proving how the differefnt technologies required in future vehicular networks are integrated in eGW and how the previously defined requirements are met. Then, a proof of concept is implemented showing the viability of the proposed concept and methodology, providing details of the experimental results. The architecture is also evaluated from a scalability point of view, looking at HW cost and power consump |
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