Design exploration and measurement benchmark of integrated-circuits based on graphene field-effect-transistors : towards wireless nanotransceivers

This doctoral thesis approaches the design requirements for future high / ultra-high data rate (from 100 Mbps to 100 Gbps) nanotransceivers (nanoTRx) applied to wireless nanonetworks which imply short/ultra-short distance ranges (3 cm ¿ 3 m). It explores graphene field-effect-transistors (GFET), by simulation against measurement benchmarks, as a potential solution for implementing large-signal high-frequency circuits, by virtue of graphene¿s one-atom thickness and high carrier-mobility extraordinary properties. Finally, the thesis discusses the challenges faced by GFETs, such as zero-bandgap and high metal-graphene contact-resistance, to be able to propose improvements for achieving the initial proposed goals. Chemical-Vapour-Deposition (CVD) GFET fabrication is considered, which is very promising for large-scale manufacturing (CMOS process compatible), and for that fast-computing large-signal compact modeling for complex circuit design is analysed in depth and optimized, and consequently a set of diverse large-signal static and dynamic GFET circuits are simulated and benchmarked against available measurements assessing the accuracy of the proposed models and deriving scaling prospects. An optimization of the current-to-voltage (I-V) characteristic of a GFET compact model, based upon drift-diffusion carrier transport, is presented. The improved accuracy at the Dirac point extends the model usability for GFETs when scaling parameters such as voltage supply (Vdd), gate length (L), dielectric thickness (tox) and carrier mobility (¿) for large-signal design exploration in circuits. The model accuracy is demonstrated through parameters fitting to measurements taken from CVD GFETs fabricated in the University of Siegen and Technical University of Milan. The script has been written in a standard behavioural language (Verilog-A), and extensively run in a commercial analog circuit simulator (Cadence environment) demonstrating its robustness. Besides a simple capacitance-to-voltage model (C-V), a small-signal parasitic capacitance model fitted to dynamic measurements for self-aligned CVD GFETs available in the literature is added, enabling to forecast maximum-frequency-of-oscillation (fmax) trends for future scaling. A design-oriented characterization of complementary inverter circuits (INV) based on GFETs is presented as well. Our proposed compact model is benchmarked at the circuit level against another compact model based on a virtual-source approach. Furthermore