Control gate length, spacing, channel hole diameter, and stacked layer number design for bit-cost scalable-type three-dimensional stackable NAND flash memory

A cell design for three-dimensional (3D) stackable NAND (3D NAND) flash memory are investigated with emphases on control gate length (Lg), spacing (Lspace) and channel hole diameter (Φ). The requirements for the Lg and Lspace are derived from the 3D device simulation and the effective cell size that competes with the planar NAND. The simulations reveal that Lg = Lspace = 20 nm (40 nm layer pitch) is achievable for bit-cost scalable (BiCS)-type 3D NAND with the 90 nm diameter hole. If the number of stacked layers is 22 with the layer pitch of 40 nm, the effective cell size of the 3D NAND corresponds to that of 15 nm planar NAND technology. Furthermore, cell characteristics of the macaroni body channel with various Φ are investigated. Although macaroni body channel improves cell characteristics at Φ = 90 nm, a cell with Φ = 60 nm without macaroni body structure shows better characteristics.