N-Channel High Speed Nonvolatile Static RAM Utilizing MNOS Capasitors

An improved n-channel nonvolatile static RAM is proposed by introducing a new memory cell which consists of a pair of MNOS capacitors and a 6-transistor MOS flipflop circuit. The RAM can be operated as a high speed static memory under a stable power supply, and as a nonvolatile memory by externally applying erasing/writing signals to a common MNOS gate signal line. Self-generation of inhibiting voltage by bootstrapping effect of MNOS capacitors enables this memory to operate with a single power supply of 5 V. Fully decoded 16-bit experimental devices are fabricated and evaluated. This technology shows the possibility to realize a high packing density memory of 4 K-bit or beyond with the access time of less than 100 ns using 3 µm design rule.