3D Packages and Assembly Methodologies

3D packaging is coming of age. Initially it was conceived to provide more memory in the same space. Memory die were stacked after thinning the die and bonding them on top of each other using conventional, thin die bond adhesive. The interconnect method remained wire bonding. While at first same die were stacked, the functionality was soon expanded by stacking different type of memory and or controllers in the same package. The explosive growth in mobile products and new applications while shrinking the form factor demanded a new packaging concept: the stacking of packages. The bottom package contains typically the application processor while top package holds memory, often stacked as well. Here, interconnects between packages are solder joints. As the demand for functionality and performance continues to grow relentlessly, bandwidth and electrical performance increase again demand more advanced packaging. It appears that silicon interposers, also called 2.5 D, will be the next type of packaging. The silicon interposer acts as a very high density substrate interconnecting die of different functionality. The interposer still requires an organic substrate as a CTE mismatch mitigator to connect to the motherboard. The ultimate step of the packaging technology evolution will be the real 3D package based on die to die interconnects based through silicon vias (TSV) providing the densest levels of interconnects between heterogeneous die and components.