Integration Technologies Transforming the World
Emergence of Die Partitioning and Chiplets • Drivers and benefits: • Moore’s law benefits are slowing at SOC level • Traditional SOC cost barriers-NPI costs inflating • SOC scaling limitations for integration of analog, logic and memory circuits • Economic leverage of trailing nodes for analog and m...
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| Veröffentlicht in: | IMAPSource Proceedings 2024-04, Vol.2020 (DPC) |
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| container_title | IMAPSource Proceedings |
| container_volume | 2020 |
| creator | Chang, Yin Rice, Rich |
| description | Emergence of Die Partitioning and Chiplets
•
Drivers and benefits:
•
Moore’s law benefits are slowing at SOC level
•
Traditional SOC cost barriers-NPI costs inflating
•
SOC scaling limitations for integration of analog, logic and memory circuits
•
Economic leverage of trailing nodes for analog and mature devices
•
Mix & match systems –time to market, system flexibility
•
Performance and cost optimization for individual chips
•
Near Monolithic & More Than Monolithic Integration better performance than SoC
•
Key Integration Technologies
•
MCM, 2.5D, 3D, Fan-out, Bridge |
| doi_str_mv | 10.4071/001c.116630 |
| format | Article |
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•
Drivers and benefits:
•
Moore’s law benefits are slowing at SOC level
•
Traditional SOC cost barriers-NPI costs inflating
•
SOC scaling limitations for integration of analog, logic and memory circuits
•
Economic leverage of trailing nodes for analog and mature devices
•
Mix & match systems –time to market, system flexibility
•
Performance and cost optimization for individual chips
•
Near Monolithic & More Than Monolithic Integration better performance than SoC
•
Key Integration Technologies
•
MCM, 2.5D, 3D, Fan-out, Bridge</description><identifier>ISSN: 2380-4505</identifier><identifier>EISSN: 2380-4505</identifier><identifier>DOI: 10.4071/001c.116630</identifier><language>eng</language><ispartof>IMAPSource Proceedings, 2024-04, Vol.2020 (DPC)</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27903,27904</link.rule.ids></links><search><creatorcontrib>Chang, Yin</creatorcontrib><creatorcontrib>Rice, Rich</creatorcontrib><title>Integration Technologies Transforming the World</title><title>IMAPSource Proceedings</title><description>Emergence of Die Partitioning and Chiplets
•
Drivers and benefits:
•
Moore’s law benefits are slowing at SOC level
•
Traditional SOC cost barriers-NPI costs inflating
•
SOC scaling limitations for integration of analog, logic and memory circuits
•
Economic leverage of trailing nodes for analog and mature devices
•
Mix & match systems –time to market, system flexibility
•
Performance and cost optimization for individual chips
•
Near Monolithic & More Than Monolithic Integration better performance than SoC
•
Key Integration Technologies
•
MCM, 2.5D, 3D, Fan-out, Bridge</description><issn>2380-4505</issn><issn>2380-4505</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNqVzj0LwjAUheGLKFi0k38gu9je2y_tLIruBccQa9oG2kRuuvjvpejg6nTe4QwPwIYwynBPMSLVEVFRpDiDIEkPuMtyzOc_vYTQe3PHJCcqy4ICiK921C2r0TgrKl131vWuNdqLipX1jePB2FaMnRY3x_1jDYtG9V6H313B9nyqjpddzc571o18shkUvyShnFhyYskPK_3v_QZebzz9</recordid><startdate>20240416</startdate><enddate>20240416</enddate><creator>Chang, Yin</creator><creator>Rice, Rich</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20240416</creationdate><title>Integration Technologies Transforming the World</title><author>Chang, Yin ; Rice, Rich</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-crossref_primary_10_4071_001c_1166303</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chang, Yin</creatorcontrib><creatorcontrib>Rice, Rich</creatorcontrib><collection>CrossRef</collection><jtitle>IMAPSource Proceedings</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chang, Yin</au><au>Rice, Rich</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Integration Technologies Transforming the World</atitle><jtitle>IMAPSource Proceedings</jtitle><date>2024-04-16</date><risdate>2024</risdate><volume>2020</volume><issue>DPC</issue><issn>2380-4505</issn><eissn>2380-4505</eissn><abstract>Emergence of Die Partitioning and Chiplets
•
Drivers and benefits:
•
Moore’s law benefits are slowing at SOC level
•
Traditional SOC cost barriers-NPI costs inflating
•
SOC scaling limitations for integration of analog, logic and memory circuits
•
Economic leverage of trailing nodes for analog and mature devices
•
Mix & match systems –time to market, system flexibility
•
Performance and cost optimization for individual chips
•
Near Monolithic & More Than Monolithic Integration better performance than SoC
•
Key Integration Technologies
•
MCM, 2.5D, 3D, Fan-out, Bridge</abstract><doi>10.4071/001c.116630</doi></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 2380-4505 |
| ispartof | IMAPSource Proceedings, 2024-04, Vol.2020 (DPC) |
| issn | 2380-4505 2380-4505 |
| language | eng |
| recordid | cdi_crossref_primary_10_4071_001c_116630 |
| source | Alma/SFX Local Collection |
| title | Integration Technologies Transforming the World |
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