Integration Technologies Transforming the World

Emergence of Die Partitioning and Chiplets • Drivers and benefits: • Moore’s law benefits are slowing at SOC level • Traditional SOC cost barriers-NPI costs inflating • SOC scaling limitations for integration of analog, logic and memory circuits • Economic leverage of trailing nodes for analog and mature devices • Mix & match systems –time to market, system flexibility • Performance and cost optimization for individual chips • Near Monolithic & More Than Monolithic Integration better performance than SoC • Key Integration Technologies • MCM, 2.5D, 3D, Fan-out, Bridge