Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETs with 3D Cellular Layouts

This work presents for the first time a comparative numerical study on the performance of planar 3.3 kV SiC MOSFETs during clamped and unclamped inductive switching for various cell layouts and pitches. It is demonstrated that despite its larger on-state losses, the atomic lattice layout (ALL) incurs smaller switching losses than the stripe and the circular designs for all examined cell pitches. Conversely, while the ALL does turn off earlier than the other layouts during UIS, the decrease in the peak lattice temperature that it brings is predicted to be marginal if just a single unit cell is considered.