Design of Self-Adaptive Weighted Neuron model using Floating Gate Technology

The paper presents an analog circuit solution for implementing models of synapses with short-term adaption, derives an analytical solution (Floating gate charge as weights) for spiking input signals, and presents simulation results using a 45nm CMOS process using floating gate technology. The circuit is suitable for integration in large arrays of integrate-and-fire neurons and thus, can be used for evaluating computational roles of short-term adaption at the network level. Proposed floating gate p channel MOSFET (FGPMOS) can self-adapt, learn and store data with help of external voltages highly precise non-volatile and stable programming of weights (training) after fabrication of circuit have been performed. On application of feedback in the circuit, short-term self-adaption with spiking input signal has been observed. The model can also demonstrate homeostatic intrinsic plasticity, spike-based algorithms, and LMS algorithms. The model has a 4.5µV/℃ temperature coefficient, 0.675µW power consumption, and consumes a chip area of about 130×90 nm2. The model is compact, low power, and stable. The proposed circuit has been applied to design a cell membrane (bio-sensor CMOS-based circuit) depicting the effect of Sodium (NA) and Potassium (K) on synaptic action. With the help of the Na and K feedback circuit, effects of polarization and depolarization on synapse output have been demonstrated and thus depict spike-timing-dependent plasticity. The work can be extended to design a complete neural architecture, an array of such complete neural cells, in turn, can design devices for assistive technology or human-like machines.