Power Optimized Design Framework for FPGA Clusters

Expectations for Multi-access Edge Computing (MEC) have been increasing in recent years and, FPGA clusters have attracted attention as a computing platform as MEC servers due to their power-saving characteristics. These FPGA clusters can improve performance by directly connecting multiple FPGAs to utilize more computing resources. However, the results of the power consumption analysis of FPGA clusters in our previous studies show that the power consumption of the interconnect between FPGAs accounts for most of the power consumption of the entire system. In this study, we propose a framework that uses an optimization-based mapping algorithm to automatically map distributed processing applications without sacrificing communication performance and disable links that are unnecessary for application execution. This framework can automatically reduce power consumption. Using this framework to run applications on multiple boards, we can reduce the power consumption of the entire system by up to 52%.