9.3: Control of Threshold Voltage in Back Channel Etch Type Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

9.3: Control of Threshold Voltage in Back Channel Etch Type Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

Tuning the process pressure at the deposition of the passivation layers has been suggested in the way of controlling the threshold voltage of a‐IGZO TFTs, making it possible to employ gate driver integration. It has showed that Vth linearly changes with the pressure ΔVth/ΔPressure∼3.5V/100Pa. A 3.2...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:SID International Symposium Digest of technical papers 2011-06, Vol.42 (1), p.104-106
Hauptverfasser: Lee, Seung Min, Ryoo, Chang Il, Park, Jae Wook, Han, Joonsoo, Kim, Dae-Won, Kim, Yong-Yub, Kang, Im-Kuk, Seo, Kyung-Han, Koh, Young Ju, Han, Dong-Min, Choi, Yong-Ho, Seo, Hyun-Sik, Kim, Bong Chul, Cha, Soo Youle, Bae, Jong-Uk, Kim, Chang Dong, Jun, Myungchul, Hwang, Yong Kee
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Tuning the process pressure at the deposition of the passivation layers has been suggested in the way of controlling the threshold voltage of a‐IGZO TFTs, making it possible to employ gate driver integration. It has showed that Vth linearly changes with the pressure ΔVth/ΔPressure∼3.5V/100Pa. A 3.2 inch WVGA AMLCD with integrated gate driver circuits were successfully demonstrated using the enhancement mode BCE type bottom gate a‐IGZO TFTs.
ISSN:0097-966X
2168-0159
DOI:10.1889/1.3621002