P-40: Design of Analog Pixel Memory Circuit with Low Temperature Polycrystalline Silicon TFTs for Low Power Application

P-40: Design of Analog Pixel Memory Circuit with Low Temperature Polycrystalline Silicon TFTs for Low Power Application

A new analog pixel memory cell realized in a 3‐μm LTPS technology is proposed to achieve low‐power consumption for TFT‐LCDs. By employing the inversion data in storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3Hz with output...

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Veröffentlicht in:SID International Symposium Digest of technical papers 2010-05, Vol.41 (1), p.1363-1366
Hauptverfasser: Chu, Li-Wei, Liu, Po-Tsun, Ker, Ming-Dou, Zheng, Guang-Ting, Li, Yu-Hsuan, Kuo, Chung-Hung, Li, Chun-Huai, Hsieh, Yao-Jen, Liu, Chun-Ting
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Sprache:eng
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Zusammenfassung:A new analog pixel memory cell realized in a 3‐μm LTPS technology is proposed to achieve low‐power consumption for TFT‐LCDs. By employing the inversion data in storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3Hz with output decay only less than 0.075V under the input data from 1V to 4V.
ISSN:0097-966X
2168-0159
DOI:10.1889/1.3499953