P-3: Scaling of a-Si TFT Gate Drivers

The characteristic feature of an optimum design of a‐Si gate driver circuits and its scaling properties are presented. The delay time of the output pulse of gate driver circuits with different layout characteristics was analyzed by a distributed‐load modeling. The effect of TFT properties, clock phase and the output load on the optimum condition is given. Finally, scaling has been found to give apparent power law dependence on the circuit area, signifying higher performance of the circuits with smaller area.