P-3: Analysis of Poly-Si TFTs' Degradation Behavior Induced by DC Stress

P-3: Analysis of Poly-Si TFTs' Degradation Behavior Induced by DC Stress

DC stress induced degradation was compared between LTPS short channel LDD NMOSFETs and PMOSFETs with a dimension of W/L = 3/3 μm/μm by degradation mapping of device parameters. Asymmetric degradation phenomena were classified for different type of devices and compared with respect to applied bias an...

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Veröffentlicht in:SID International Symposium Digest of technical papers 2005-05, Vol.36 (1), p.232-235
Hauptverfasser: Lee, Seok-Woo, Kang, HoChul, Oh, Kum Mi, Kim, Eugene, Park, Soo-Jeong, Lim, Kyoung Moon, Kim, Chang-Dong, Chung, In-Jae
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container_end_page 235
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container_start_page 232
container_title SID International Symposium Digest of technical papers
container_volume 36
creator Lee, Seok-Woo
Kang, HoChul
Oh, Kum Mi
Kim, Eugene
Park, Soo-Jeong
Lim, Kyoung Moon
Kim, Chang-Dong
Chung, In-Jae
description DC stress induced degradation was compared between LTPS short channel LDD NMOSFETs and PMOSFETs with a dimension of W/L = 3/3 μm/μm by degradation mapping of device parameters. Asymmetric degradation phenomena were classified for different type of devices and compared with respect to applied bias and power.
doi_str_mv 10.1889/1.2036411
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title P-3: Analysis of Poly-Si TFTs' Degradation Behavior Induced by DC Stress
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