P-3: Analysis of Poly-Si TFTs' Degradation Behavior Induced by DC Stress

DC stress induced degradation was compared between LTPS short channel LDD NMOSFETs and PMOSFETs with a dimension of W/L = 3/3 μm/μm by degradation mapping of device parameters. Asymmetric degradation phenomena were classified for different type of devices and compared with respect to applied bias an...

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Veröffentlicht in:	SID International Symposium Digest of technical papers 2005-05, Vol.36 (1), p.232-235
Hauptverfasser:	Lee, Seok-Woo, Kang, HoChul, Oh, Kum Mi, Kim, Eugene, Park, Soo-Jeong, Lim, Kyoung Moon, Kim, Chang-Dong, Chung, In-Jae
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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Zusammenfassung:	DC stress induced degradation was compared between LTPS short channel LDD NMOSFETs and PMOSFETs with a dimension of W/L = 3/3 μm/μm by degradation mapping of device parameters. Asymmetric degradation phenomena were classified for different type of devices and compared with respect to applied bias and power.
ISSN:	0097-966X 2168-0159
DOI:	10.1889/1.2036411