Effects of Numerical Method Selection on Fully-Pipelined FPGA Accelerators for Neural Simulations

The neural simulation is a method that mimics features and functionalities of biophysical brains and reproduces these on computers. Adjusting parameters properly, all activities of neurons are able to be simulated based on equations derived by the underlying neuron model. Neuron models are represent...

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Veröffentlicht in:IEICE Transactions on Information and Systems 2024, pp.2024EDP7022
Hauptverfasser: ZHOU, Xiaoxiao, SATO, Yukinori
Format: Artikel
Sprache:eng ; jpn
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Zusammenfassung:The neural simulation is a method that mimics features and functionalities of biophysical brains and reproduces these on computers. Adjusting parameters properly, all activities of neurons are able to be simulated based on equations derived by the underlying neuron model. Neuron models are represented by ordinary differential equations, and generally solved numerically on computers. In this paper, we focus on designing a dedicated FPGA accelerator that solves a numerical method for neural simulation, and evaluate the trade-off between performance and accuracy when we implement two different numerical methods, Euler method and Runge-Kutta method. Here, Euler is known to be a simple and easy to implement method while Runge-Kutta is a compute-intensive but more precise numerical method. We compare the performance of these FPGA accelerators for a neural network consisting of 32,768 neurons. From the results, we confirm that we can successfully realize fully-pipelined dedicated solvers on a single FPGA board. Further, the FPGA implementation of Runge-Kutta method achieves 9.92x performance gain compared with Euler method with the same accuracy. Compared with the baseline less-accurate Euler method, the FPGA-based Runge-Kutta is 1.98 times faster while the CPU implementation of it is 1.53 times slower than the baseline of Euler method. This trade-off among performance and accuracy on FPGA implementation is unique and differs from typical results seen in typical implementation on general-purpose CPUs.
ISSN:0916-8532
1745-1361
DOI:10.1587/transinf.2024EDP7022