An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis

An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip int...

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Veröffentlicht in:IEICE Transactions on Electronics 2016/04/01, Vol.E99.C(4), pp.440-443
Hauptverfasser: LEE, Pil-Ho, HWANG, Yu-Jeong, LEE, Han-Yeol, LEE, Hyun-Bae, JANG, Young-Chan
Format: Artikel
Sprache:eng
Schlagworte:
analog-to-digital converter
chip-to-chip interface
on-chip monitoring circuit
phase-locked loop-based frequency synthesizer
sub-sampling
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Beschreibung
Zusammenfassung:An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.
ISSN:0916-8524
1745-1353
DOI:10.1587/transele.E99.C.440