Efficient event processing through reconfigurable hardware for algorithmic trading

In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for high-frequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware---FPGAs---to achieve line-rate processing. Furthermore, ou...

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Veröffentlicht in:Proceedings of the VLDB Endowment 2010-09, Vol.3 (1-2), p.1525-1528
Hauptverfasser: Sadoghi, Mohammad, Labrecque, Martin, Singh, Harsh, Shum, Warren, Jacobsen, Hans-Arno
Format: Artikel
Sprache:eng
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Beschreibung
Zusammenfassung:In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for high-frequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware---FPGAs---to achieve line-rate processing. Furthermore, our event processing engine supports Boolean expression matching with an expressive predicate language that models complex financial strategies to autonomously buy and sell stocks based on real-time financial data.
ISSN:2150-8097
2150-8097
DOI:10.14778/1920841.1921029