Cascaded VLSI neural network chips: Hardware learning for pattern recognition and classification

Currently map data is stored as high- resolution digitized pixel data on CD-ROM storage devices. The copious amount of data generated from the global map data base overwhelms even high-density optical storage methods. In addition, the map user is concerned not with the high-resolution image of the map, but the actual features such as roads and rivers. By classifying the map-image pixels into separate features, the dimensional ity of the data is dramatically reduced, the map is significantly decluttered, and the data is in the form most suitable for further analysis. Because of the extensive volume of the data already stored and its on-demand nature, classification speed must exceed the CD-ROM read speed so that access rates are unaffected. This paper describes a neural network approach to pattern classification applied to map pixel data. Software simulations of a sophisticated neural network show that neural networks are indeed equivalent to optimal statistical pattern classifiers. Furthermore, a fully parallel neural network hardware implementatiort developed at JPL, surpasses the necessary processing speed, and provides high classification accuracy. Our software as well a hardware results are presented in this paper along with a brief backgrourtd in pattern classification and neural networks.