Initial Virgin Erase State Engineering for Highly Reliable 2D & 3D NAND Flash Memory

Over the past 30-40 years, to enhance the integration density of NAND flash, the size of the Cell Transistor(TR) has been reduced in 2-dimensional (2D) structures, and stacking has been employed in 3D structures. The improvement in integration density has led to data loss due to interference between Cell TRs, and to address this, materials, processes, and logic have been improved, but there are limitations. Interference phenomena caused by Cell TR interference are a major factor reducing the reliability of NAND flash. This study confirms the importance of the initial Virgin Cell TR Vth in the reliability of NAND flash. In 2D structures, reducing the size of Cell TR enhances the coupling effect of adjacent Cell TRs, making it appear that they have different electrons originally stored. In 3D structures, the increase in stacked Cell TRs induces a decrease in Cell current, leading to increased interference between adjacent Cell TRs in the vertical direction. Incorrect changes in Cell TR Vth not only result in data loss but also worsen the reliability under Cycle and Retention conditions. The degree of Cell interference confirmed through simulation can be used to assess the extent of data loss in various patterns of Cell TR states. Quantifying data loss through various patterns reveals that erased Cell TRs are weak. However, for Cell TRs with a high initial Virgin Vth, interference between programmed Cell TRs worsens. In a well-designed 3D structure, interference from erased Cell TRs is relatively good, but reliability is equally degraded. The importance of the initial Virgin Cell TR Vth has been confirmed through verification of Cell TR size differences. To reduce interference between Cell TRs, an optimized initial Virgin Cell TR Vth is essential. A low Virgin Cell Vth induces a relatively high Program environment, increasing the interference effect between programmed Cell TRs. A high Virgin Cell Vth causes erased Cell TRs to receive strong interference from adjacent programmed Cell TRs, leading to defects. Therefore, an optimized Virgin Cell TR Vth can minimize degradation even under Cycle and worst-case Retention conditions. The initial erase state of Cell TRs has been identified as the most critical factor in interference phenomena, providing an important benchmark for future NAND flash research. we suggest a design standard for the next generation of 3D NAND flash cell transistors from cell disturb and retention. Figure 1