(Digital Presentation) Selective SiGe Vapor Etching Using Br 2 in View of Nanosheet Device Isolation

Forksheet transistors are lateral nanosheet devices with a forked gate structure [1,2]. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the epitaxial growth of Si/Si 1-y Ge y /multi-{Si 1-x Ge x /Si} epi stacks (y>x) where the bottom Si 1-y Ge y layer is later replaced by a SiN/SiCO isolation [4]. The fabrication scheme relies on selective etching of the sacrificial Si 1-y Ge y layer with respect to the {Si 1-x Ge x /Si} multi-stack. Owing to the very small dimensions (e.g. sub-10 nm nanowire channel diameter), high etch selectivity towards both Si 1-x Ge x and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4] as well as on the etch process itself (high selectivity, limited Si 1-x Ge x and Si consumption) [5-7]. The selective Si 1-y Ge y removal requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers [4-6]. Also, HCl-based vapor etching has been reported for SiGe removal, with high selectivity towards Si [7]. The HCl vapor etching requires a sufficiently high process temperature (typically ≥ 600°C). This makes it less attractive for fabrication schemes with bottom isolations. The presence of the Ge-rich Si 1-y Ge y layer in the as-grown epi stack results in an enhanced risk for unwanted layer relaxation. A low temperature Br 2 -based vapor etching process is proposed as an alternative for the selective Si 1-y Ge y removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br 2 etching enables high etch selectivity of Si 0.5 Ge 0.5 towards Si and Si 1-x Ge x (x=0.2, 0.23, and 0.3). Figure 1 compares the etching characteristics