(Invited) Sub-40mV Sigma V TH Igzo nFETs in 300mm Fab

In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO 2 , Al 2 O 3 and HfO 2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO 2 shows a large recovery while for Al 2 O 3 and HfO 2 , it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for I OFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x10 7 Ohm.cm 2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO 2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO . The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O 2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occ