Impact of Contact Doping on Electrical Characteristics in WSe 2 FET

Since layered semiconductor tungsten diselenide (WSe 2 ) has no dangling bond and a relatively large band gap, it is expected as a channel material for an application of field effect transistor (FET)[1]. On the other hand, high energy process destroys the crystal structure of the layered semiconduct...

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Veröffentlicht in:Meeting abstracts (Electrochemical Society) 2020-11, Vol.MA2020-02 (24), p.1727-1727
Hauptverfasser: Matsuzaki, Takahiro, Kawanago, Takamasa, Oda, Shunri
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Sprache:eng
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Zusammenfassung:Since layered semiconductor tungsten diselenide (WSe 2 ) has no dangling bond and a relatively large band gap, it is expected as a channel material for an application of field effect transistor (FET)[1]. On the other hand, high energy process destroys the crystal structure of the layered semiconductor. In this context, carrier doping by the low energy process is important for improving the electrical characteristics. This study reports that CYTOP (9 wt%) was applied as a doping material on the WSe 2 FET for p-type operation by spin coating and the impact of contact doping on the electrical characteristics was investigated. A SiO 2 gate dielectric was formed on a heavily-doped p-Si substrate (p+-Si) using thermal oxidation for back-gate structure. Next, a source / drain of Au (40 nm) / Ti (10 nm) was prepared by using photolithography and lift-off. Using a PDMS stamp and a micromanipulator, WSe 2 , which was mechanically peeled off using Scotch tape, was transferred between the source and drain to fabricate a back-gate WSe 2 FET. After measuring the electrical characteristics without CYTOP, CYTOP was applied on the WSe 2 FET surface using a spin coating. Then, the electrical characteristics with CYTOP were measured again. In this study, the annealing was performed for 30min at 200 ° C and 250 ° C. I d -V g characteristics as a function of annealing temperature of the fabricated back gate WSe 2 FET are shown in Fig. 1. From the Fig. 1, it can be confirmed that WSe 2 FET shows p-type operation. Moreover, it can be confirmed that the drain current increases by applying the CYTOP, while the low drain current was observed without CYTOP. It was found that the drain current was increased with increasing the annealing temperature. [Acknowledgments] The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616). [References] [1] In-Tak Cho et al., Applied Physics Letters 106, 023504 (2015). Figure 1
ISSN:2151-2043
2151-2035
DOI:10.1149/MA2020-02241727mtgabs