Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al 2 O 3 -Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In 0.53 Ga 0.47 As channel, where the SiO 2 insulator in [1] is replaced by a wider bandgap p-type In 0.52 Al 0.48 As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (N d ) present in the channel of a JL MOSFET is less problematic for In 0.53 Ga 0.47 As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm 2 /V·s at N d = 1×10 19 cm -3 , while in In 0.53 Ga 0.47 As the bulk mobility is ~4,000 cm 2 /V·s at a similar N d level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n - In 0.53 Ga 0.47 As (N d = 2×10 18 cm -3 ) on a 500-nm-thick p -In 0.52 Al 0.48 As (N a = 8×10 15 cm -3 ) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In 0.53 Ga 0.47 As layer was thinned using a 10% H 2 O 2 /10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH 4 ) 2 S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al 2 O 3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al 2 O 3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H 2 +90%N 2 ) with additional heating of the sample holder (up t