AlGaN/GaN High Electron Mobility Transistors with a p-Type GaN Cap Layer

In the past few years, GaN based materials are widely used for power devices. It seems to be expected to replace silicon in the position of power devices with high operation frequency and power density. Currently in the applications of GaN based power transistors, AlGaN/GaN heterostructurs with high 2DEG concentration and high electron mobility show the low on-resistance. Moreover, due to the wide band-gap in GaN based materials, devices can be operated at high voltage. However, these devices have surface and buffer-related problems which cause current collapse phenomenon. Some publications with analysis models based on the electron trapping by surface states have been proposed. In this study, AlGaN/GaN HEMTs with different p-GaN cap structures are investigated in the gate leakage, breakdown voltage and dynamic on-resistance. The epitaxial layers of AlGaN/GaN HEMTs were grown by MOCVD including a ~3900-nm buffer layer, a 300-nm GaN channel layer, an 1-nm AlN spacer layer, a 20-nm Al 0.25 Ga 0.75 N and a p-GaN cap layer. Three different p-GaN cap layers were investigated. In structure A, the Mg doping concentration was 1´10 19 cm -3 and thickness of p-GaN cap layer is 5-nm. In structure B, higher Mg doping concentration (3´10 19 cm -3 ) but the same thickness (5-nm) of p-GaN cap was used. In structure C, thicker p-GaN cap (8-nm) with Mg doping concentration (3´10 19 cm -3 ) was used. To evaluate the effect of p-GaN cap layer on device performance, Schottky gate devices with different p-GaN cap layers were fabricated simultaneously for comparison. Before device fabricating, all samples were activated in nitrogen atmosphere at 700°C for 15 minutes. After activation, mesa isolation was etched by ICP down to the buffer layer. Both source and drain ohmic contacts were made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) and annealed at 875°C in a nitrogen atmosphere for 40 s. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metals were used to form Schottky gate. The devices were passivated by a 200-nm SiN. Devices fabricated using structures A, B and C were designated as device A, B and C, respectively. The Hall measurement results showed that structure A had lowest sheet resistance after activation. The values are similar to those obtained from TLM measurement. The sheet resistance from TLM measurement were 269, 273, and 307 W/sq for the device A, B and C after activation. The drain current (I D ) of device A is lower than the device B and device C at V DS = 10 V due t