(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1]. These devices continue to be the subject of many innovations but face increasing scaling challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing their ultimate scaling limit and being one of the most promising candidates to further support the CMOS roadmap (Fig. 1) [2-5]. In this work, we address some of the challenges faced by these 3D devices, focusing first on the impact of thermal and plasma treatments at gate module [6]. J G and noise can be substantially reduced, without EOT penalty, with a post HfO 2 deposition anneal (PDA) and F incorporation in the gate stack by SF 6 . The latter can also improve the mobility and reduce N it , mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while also allowing a simplified dual-effective work-function (EWF) metal CMOS scheme where optimized cleans are key. PDA improves the bias-temperature-instability lifetime and hot-carrier immunity via reduction of bulk defects. Furthermore, the doping scheme and EWF metal can also be used to engineer the interface properties. Indeed, improved reliability and LF noise have been reported for junctionless (JL) GAA-NWFETs [4], with S VG .f of inversion-mode (IM) GAA-NWFETs showing more uniform oxide trap density profiles, as a function of depth, for TiAl-based vs. TiN EWF metals [7]. Extensionless IM or JL can also help to enlarge process robustness by ensuring a smaller E ox increase at the bottom-gate edges from the fins release process for lateral GAA-NWFETs formation [4]. These devices are closer to finFETs regarding layout and processing, but vertically stacked lateral NWs will be needed for them to be competitive in performance per footprint, with the drawback of increased parasitic capacitances [3]. Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up