(Invited) A Brief History of Selective Epitaxy (at IBM SRDC)

Over more than a decade—and half a dozen technology nodes—selective expitaxy has consistently been a major performance element, propelling logic devices to their ultimate targets. Throughout this period (the “Epi Renaissance”), a huge variety of epitaxial processes have been evaluated across the semiconductor industry. Because each technology generation has unique constraints and process assumptions, these epitaxy processes have varied significantly in shape, size, and composition. And of course not all survived to be implemented in full production. This presentation gives a retrospective survey of each of these epitaxial processes, ranging from a simple, single undoped Si raised source/drain to multi-pass growth with complex multi-layer film stack. Selective epitaxy at IBM SRDC began with an undoped selective Si raised source drain (RSD) at the 90nm technology node, used to improve the silicide formation and placement. This was a key enabling feature of the Si on SiGe on insulator (SGOI) technology [1]. Since the silicide had difficulties with the SiGe underlayer, a selective epitaxial Si solution allowed significantly improved contact resistance. SGOI showed great promise on long channel devices, and due to the uniaxial nature of the strain it showed a clear performance benefit on both NFET and PFET. Unfortunately, the short channel devices were consistently degraded, so for the ultimate performance targets IBM instead turned to stressed nitride liners to deliver channel strain [2], while Intel introduced embedded SiGe source/drain (eSiGe) [3]. IBM incorporated eSiGe as a PFET performance element starting at the 65 nm node. However, instead of an in-situ boron doped eSiGe grown just prior to silicide (late eSiGe) similar to what Intel had published, IBM used a lower %Ge, undoped SiGe film grown just after gate module (early eSiGe). Early eSiGe was effectively a “drop-in” solution that allowed for minimal disruption to the existing integration and device design while still providing significant performance gains via channel strain [4]. For the 45nm node IBM published a novel method called Hybrid Orientation Substrate (HOT) that enabled PFET performance gain by changing the PFET Si crystal orientation from to . This method utilized a SOI wafer with top Si layer bonded to a handle wafer. At the beginning of the process, the PFET regions were etched down through the buried oxide, and a thick, undoped selective Si epi was then re-grown on the substrate. In co