(Invited) Reliability of SiGe HBTs in Long-Term Operation

Introduction In the ongoing development towards RF circuits with still higher operation frequencies SiGe HBT technologies continuously have to prove their competitiveness against advanced Si CMOS and compound semiconductor millimeter-wave circuits. Yet, besides excellent RF performance at circuit operation frequencies – meanwhile even well beyond 100 GHz –customer focus is also put on operating constraints (“safe operating area”, SOA) and long-term reliability of the devices. If the HBT power load in a circuit stays within the SOA limits but collector voltage surpasses open-base breakdown voltage (BV CEO ) or the emitter-base (EB) diode is reverse biased a gradual decrease of the HBT current gain (“beta ageing”) can usually be observed (Fig. 1a). This beta degradation is correlated to an increase of the base recombination current caused by recombination centers (“traps”) at dielectric interfaces. These again are being created by hot carrier injection (“HCI”). This interface trap generation and the gradual character of ageing are in contrast with device failure of III-V devices where defects are generated inside the semiconductor and failure shows more abrupt and end-of-life characteristics [1]. Concerning HBT reliability the questions to address then are: What is the maximum HBT beta degradation tolerable for any specific circuit operation? Will it stay within this limit during the anticipated circuit life-time (up to 20 years for space applications)? Our intention therefore was to develop an ageing function which describes base current change or beta degradation, respectively, as function of electrical stressors, ambient temperature, and stress time. The experimental setups to evaluate ageing are forward and reverse bias stress conditions which we applied for up to 1000h and in a temperature range from -40°C up to 150°C. Operation Constraints The SOA to which device operation should be restricted can be derived from the common-base output characteristics which indicate device instabilities by current pinch-in or electro-thermal runaway. For low-voltages electro-migration will define maximum current densities. The latter can to be avoided be defining proper design guidelines for the metal line layout. Interface Defect Generation and Annihilation Even within SOA sufficiently high electrical fields in the collector-base (CB) space charge region will trigger avalanche carrier multiplication there and part of them will be accelerated towards EB and CB spacer o