Impact of Gate Dielectric Geometry on the Nanowire MOSFETs Performance and Scaling

(1)A 2D tunneling model is developed to assess the tunneling reduction in cylindrical gate (CG) in nanowire (NW) MOSFETs with radius Rs, comparing with the planar double gate (PG-DG) transistor with Tsemi=2Rs and same dielectric thickness Tox. High-k gate dielectric is more effective to suppress the gate leakage in NW than in PG transistors, (2) the carrier quantization induced tunneling barrier reduction is larger in NW than in DG-PG transistors. The gate tunneling rate is finally determined by combining two effects of (1) and (2). Different results for Si, Ge, and InGaAs NWs are demonstrated, (3) comparing with PG transistor, the overdrive gate voltage in NW transistor can be reduced significantly. At the same time evolution of dielectric charge generation, the NW transistor lifetime can be greatly extended.