(Invited) Strain Scaling and Modeling for FETs

Stress engineering overview is given including the reasons behind its ongoing evolution. Some aspects of the stress-induced defect formation are discussed. Guidelines for avoiding such defects are proposed based on stress evolution in and around transistors during the process flow. Stress-induced performance is addressed with the focus on conversion of stress-enhanced mobility into stress-enhanced on-state current. FinFET-specific stress engineering is analyzed as well as the stress vs capacitance trade-offs. Usage of simulation tools for optimization of various stress-related design trade-offs is demonstrated. It is concluded that it is a pursuit of beneficial stress patterns that improve transistor performance without creating defects and increasing variability that defines evolution of stress engineering techniques.