Structural and Electrical Analysis of Thin Interface Control Layers of MgO or Al 2 O 3 Deposited by Atomic Layer Deposition and Incorporated at the High-k/III-V Interface of MO 2 /In x Ga 1-x As (M = Hf|Zr, x = 0|0.53) Gate Stacks

Control of the high-k/III-V interface by deposition of thin (~1-2 nm) interface control layers (ICLs) of Al 2 O 3 or MgO, as part of an overall bi-layer structure with a high-k metal oxide MO2 (M = Hf|Zr), is explored. An Al 2 O 3 or MgO ICL is deposited on unpassivated InxGa1-xAs (x = 0|0.53) substrates prior to MO2 gate oxide deposition, forming a Pd/high-k/ICL/III-V gate stack. The aim of a bi-layer structure is to enable continued device scaling using a high-k MO2 oxide while improving the high-k/III-V interface quality and interfacial band structure, with an Al 2 O 3 or MgO ICL. Metal-oxide-semiconductor capacitor (MOSCAP) devices with an Al 2 O 3 ICL on p-GaAs display significantly reduced leakage current density, and reduced frequency dispersion of accumulation capacitance when compared to a no-ICL device, indicating an improved high-k/III-V band structure and interface quality, respectively. Further studies on ZrO2/Al 2 O 3 /In0.53Ga0.47As devices find a reduced defect response with a post-metal forming gas anneal.