High Yield Patterning with Simplified DFM Rules in Sub-100nm Process Technologies

Traditional DFM methods of sub-100nm technologies have emphasized on the offering of optical proximity effect driven DFM rules for designers to reduce shape variations of the conducting patterns. This offering has been complicating over the rolling-out of new technologies in the past. The complication is most severe with the semiconductor foundries, which manufacture many different designs with the same set of tools. However, not only are the DFM rules an increasing work load, but recent reports also found new manufacturing failures are produced due to the shape changes on the design required by the DFM rules. A new DFM methodology that eliminates such problems is therefore necessary. In this paper, we show how we have achieved DFM in patterning with a significantly simplified set of DFM rules in our sub-100nm technology nodes. We have used photoresist with low activation energy and sensitive PEB properties to achieve high K1 values, and thus eliminating the need of most optical proximity effect driven rules. We also adopt an OPC flow that detects over-varying shapes and automatically performs incremental fix. These technologies simplify the DFM rules and minimize the number of the new problems coming from the traditional DFM method adopted by most foundries. We have achieved better than 90% for various logic and SoC products steadily.