A Study of Stress Technology for 65nm Generic CMOS Technology

For deep sub-100nm CMOS technology, the stress level impacts transistor performance significantly. In this paper, we present the investigation results of stress technology in a 65 nm generic process. We studied some mobility enhancing technologies such as Stress-Memorization Technology (SMT) and Dual Stress Liner (DSL) process in a conventional 65 nm Generic CMOS process. The transistor performance with different stress layers and stress levels are reported. The experimental results show that SMT and higher stress level tensile ESL (Etch-Stop Layer) improve NMOS performance while compressive ESL improve PMOS significantly. For the required-device performance, the stress layer and stress architecture should be carefully optimized. The stress technology reported in this paper has been successfully implemented in the production of 65 nm generic process.