Optimizing the Interface of Spin-on Oxide and the Active Area of Transistor in Sub70nm DRAM Structures For Better Electrical Performance

The goal of this work is to investigate the interface between the active area (AA) and Spin-on oxide to improve device properties. Various liners, like oxide/nitride liners were deposited prior to spin-on oxide and several annealings were done, including ultra-violet (UV) treatment to fabricate a cleaner interface between the dielectric and the active areas. The role of liners is also to protect and reduce Si consumption during annealings in an oxidizing atmosphere. The impact of these liners on electrical parameters is discussed in this paper.