Sidewall Dislocations in Embedded SiGe Source/Drain Areas of MOSFETs and Their Impact on the Device Performance

Strain-engineered PMOS devices have been characterized by physical and electrical analysis, and computer modeling. Characteristic defects at the sidewall of embedded SiGe were found to degrade transistor performance. This could be attributed to carrier scattering rather than stress relaxation.

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Bibliographische Detailangaben
Hauptverfasser: Kammler, Thorsten, Peidous, Igor, Wei, Andy, Reichel, Carsten, Heinemann, Stefan, Romero, Karla, Engelmann, Hans-Juergen
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:Strain-engineered PMOS devices have been characterized by physical and electrical analysis, and computer modeling. Characteristic defects at the sidewall of embedded SiGe were found to degrade transistor performance. This could be attributed to carrier scattering rather than stress relaxation.
ISSN:1938-5862
1938-6737
DOI:10.1149/1.2355866