(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS

The performance of an HBT is primarily influenced by 1D dopant profile obtained by CVD epitaxy. Typically, three epitaxial layers are required to construct an HBT: the collector, the intrinsic base, and the emitter. Collector layer can be grown by either NSEG or selective epitaxy. While the NSEG process is cost effective, it results in autodoping. Switching to selective epitaxy can mitigate autodoping but must be controlled to minimize faceting. The intrinsic base is critical to device performance, with boron positioning being a key factor. Incorporating substitutional carbon atoms into the SiGe lattice significantly reduces boron diffusion. By switching from SiH 4 to Si 2 H 6 , three times more substitutional carbon incorporation in SiGe without interstitial C atoms at 550 °C is achieved. Below 600 °C, the co-flow approach is ineffective, necessitating a cyclic deposition-etch (CDE) approach to maintain selectivity. Comparisons between CDE and single deposition-etch (DE) approaches show that CDE degrades the monocrystalline SiGeC:B layer, resulting in high RMS roughness and degraded morphology. In contrast, the DE approach shows promising results with lower RMS roughness and no significant morphological degradation. The last epitaxial layer discussed is the emitter. Current fabrication methods involve non-selective Si:As deposition at growth temperatures above 600 °C, resulting in polycrystalline Si:As deposition on dielectrics and monocrystalline Si:As growth on silicon. A novel process developed at 550 °C using Si 2 H 6 as silicon precursor yields monocrystalline emitter by amorphous deposition on dielectrics followed by solid phase epitaxial regrowth. However, this process exhibits TED of arsenic, making it currently not viable.