Low Temperature Cyclic Deposition/Etch (CDE) of Tensile-Strained Si:P

Our aim was to assess the feasibility of the Low Temperature Cyclic Deposition / Etch (CDE) of tensile-Si:P for use in Raised Sources and Drains of n-type Field Effect Transistors. We were targeting high amounts of tensile strain and low resistivities in tensile Si:P layers grown at 550°C, with (i) mainstream Si 2 H 6 + PH 3 gases for the non-selective deposition of t-Si:P and (ii) HCl + GeH 4 for the selective etches of poly-Si:P versus monocrystalline Si:P (to have selectivity on patterned wafers). Thanks to the use of 10 cycles CDE processes with various HCl + GeH 4 etch durations on bulk and SiN-covered Si substrates, we showed that an etching selectivity of ~6 could be expected, for a-Si:P over t-Si:P, on patterned wafers. The presence of numerous nuclei on SiN-covered substrates nominally free of any bi-dimensional a-Si:P layers was evidenced by haze measurements, however, hinting at a lower effective selectivity. We then switched over to patterned SOI wafers with gates. We succeeded, when using 7 cycles CDE processes, in having almost full selectivity with 60s depositions and 40s etches / cycle, respectively. Maybe because there was a mix of a-Si:P and t-Si:P regions on such wafers, we had almost the same deposited t-Si:P thickness / CDE cycle (4.1–4.2 nm) whatever the HCl + GeH 4 duration / cycle in the 15s–40s range. Meanwhile, there was a gradual disappearance of a-Si:P nuclei on dielectrics together with an “apparent” P concentration reduction from 4.0% down to 2.5% as that etch duration increased.